The GN4124 is a four lane PCI Express to local bus bridge that is designed to work as a companion for low-cost FPGA devices to provide a complete bridging solution for general applications. In addition to a 4-lane PCI Express compliant PHY interface, the GN4124 also contains the data link and transaction layers, and an applications interface that is ideally suited to FPGA interfacing using a small number of pins.

Since the PCI Express transaction/link IP is hard-wired into the GN4124, there is no need to license PCIe IP. The level of integration and very low power operation of the GN4124 make it an ideal alternative to using a PIPE PHY, where IP licensing and the cost of FPGA resources and power consumption is unattractive by comparison. Using the GN4124 allows FPGA resources to be spent on what differentiates the product rather than on implementing the PCI Express protocol.

Key benefits of the GN4124:

• Supports true bi-directional traffic
• Easy to use with a pin-efficient attachment interface to low-cost FPGA devices
• Features an FPGA bitstream loader that enables configurable computing and in-field firmware upgrade
• Live on power up without FPGA programming
• Provided with royalty-free FPGA local bus IP

A turn-key Reference Design Kit is available with Gennum supplied FPGA IP:

FPGA IP

• Master/Target Controller
• Scatter/gather DMA supports up to 512 channels
• Easy attachment to customer application IP
• Royalty free source code available

Software

• Jungo based driver and example application code
• DirectShow driver/filter
• Source code available

RDK Board

• GN4124 + Spartan 3A 1400
• On board DDR SDRAM
• Connects to SDI transmitter/receiver RDK for video capture
• Schematics, board layout available

• 4 Lane PCI Express interface
  • Complies with PCI Express Base Specification 1.1
  • On-chip PHY, transaction, and link layer eliminates the cost of IP licensing
  • 2 hardware virtual channels supported
  • Payload size of up to 512 bytes with up to 4 outstanding transactions in each direction
  • Supports 3-64 bit Base Address Registers
  • Provides flexible power management capability
• Provides pin efficient local bus interface for easy attachment to popular low-cost FPGA devices
  • Uses SSTL dual data rate I/O for high-speed data transfer (16 lanes and 800MB/s in each direction)
  • FPGA source code provided for 64 bit master/target read/write buses for easy user logic attachment
  • Local bus may be operated asynchronously to the PCIe clock rate for power optimization
• "Live" on power up
  • On-chip type 0 PCI configuration space enables auto detection without FPGA activity
  • On-chip extended configuration space supports power management, serial number, MSI, and PCIe capability registers
• FPGA bitstream loader
  • Allows easy configuration of the attached FPGA through PCIe
  • Provides on-the-fly FPGA reconfiguration capability
• I2C master/target
  • Master mode allows PCI configuration space defaults to be loaded from a small E2PROM upon system reset
  • Target mode allows internal registers to be accessed from an external circuit
• 2kV ESD protection
• 256 pin 17mm x 17mm lead-free BGA
• <900mW power consumption during sustained operation
• 0-85°C operating temperature

Configurable Computing
With an on-chip FPGA Configuration Loader (FCL), the GN4124 enables configurable computing applications that use FPGA to implement algorithms. The FCL supports all mainstream low-cost and feature rich FPGA families. Efficient data interchange between the host CPU and the accelerator is assured by the high-throughput local bus interface on the GN4124. The FlexDMA FPGA IP from Gennum simplifies the attachment of the application accelerator block to the system.

HD Video Capture
By combining the GN4124 PCI Express-to-local bus endpoint bridge with the GS297x family of SDI receivers/transmitters, HD video capture and playout is achieved. To further accelerate time-to-market for this application, Gennum provides FPGA IP and example DirectShow filter driver code.

Data Acquisition
Data acquisition over PCI Express is easily implemented with the GN4124 and FlexDMA FPGA IP. The FlexDMA IP core from Gennum supports up to 256 channels of scatter/gather DMA in each direction (512 total). Since the GN4124 provides full duplex traffic via the local bus, simultaneous inputs and outputs can take advantage of the full duplex nature of PCI Express.

DSP Based Accelerator via PCI Express
Using the GN4124 and a low-cost FPGA, interfacing DSP processors to PCI Express is simplified. Either the External Memory Interface (EMIF) or Host Processor Interface (HPI) (or both) may be used as the access point to the DSP. The FlexDMA FPGA IP core provided by Gennum provides a DMA master interface and target interface. Using the EMIF interface, the target controller of the Gennum FPGA IP can be used to map DSP memory into the address space of the host controller. This same approach can be used to map the HPI interface into host address space. For high-bandwidth, low host processor overhead data movement, the scatter/gather master mode DMA of the FlexDMA can be used to shuttle data between the host and EMIF/HPI interfaces.

• High-speed data acquisition
• High definition video capture/playout
• Machine vision
• High-speed networking

Product Brief
GN4124 x4 PCI Express to Local Bus Bridge
  PDF (954.6 KB)

More information, including DataSheet, Reference Design Kit HW/SW is available at the MyGennum support portal