GS9090A
270Mb/s reclocking deserializer with an internal FIFO
Description
Features
Applications
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The GS9090A is a 270Mb/s reclocking deserializer with an internal FIFO. When used in conjunction with one of Gennum's SDI Cable Equalizers, a receive solution for SD-SDI and DVB-ASI applications can be realized.
In addition to reclocking and deserializing the input data stream, the GS9090A performs NRZI-to-NRZ decoding, descrambling as per SMPTE 259M-C, and word alignment when operating in SMPTE mode. When operating in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream.
The integrated reclocker features a very wide Input Jitter Tolerance, and is fully compatible with both SMPTE and DVB-ASI input streams.
The GS9090A includes a range of data processing functions such as error detection and correction, automatic standards detection, and EDH support. The device can also detect and extract SMPTE 352M payload identifier packets and independently identify the received video standard. This information is read from internal registers via the host interface port.
TRS errors, EDH CRC errors, and ancillary data checksum errors can all be detected and corrected. A single DATA_ERROR pin is provided which is an inverted logical 'OR'ing of all detectable errors. Individual error status is stored in internal 'ERROR_STATUS' registers.
The GS9090A also incorporates a video line-based FIFO. This FIFO may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, MPEG packet extraction and clock rate interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed format, with the associated parallel clock output signal operating at 27MHz.
The GS9090A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS compliant).
- SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding (with bypass)
- DVB-ASI sync word detection and 8b/10b decoding
- Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet extraction and clock rate interchange, and ancillary data packet extraction
- Integrated VCO and reclocker
- Automatic or manual selection between SMPTE video and DVB-ASI data
- Single serial digital input buffer with wide input sensitivity and common mode point
- User selectable additional processing features including:
- TRS, ANC data checksum, and EDH CRC error detection and correction
- programmable ANC data detection
- illegal code remapping
- Internal flywheel for noise immune H, V, F extraction
- Automatic standards detection and indication
- Enhanced Gennum Serial Peripheral Interface (GSPI)
- JTAG test interface
- Polarity insensitive for DVB-ASI and SMPTE signals
- +1.8V core power supply with optional +1.8V or +3.3V I/O power supply
- Small footprint (8mm x 8mm)
- Low power operation (typically 145mW)
- Pb-free and RoHS compliant
SMPTE 259M-C Serial Digital Interfaces; DVB-ASI Serial Digital Interfaces
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