GS9021A
EDH Coprocessor
Description
Features
Applications
Downloads
The GS9021A implements error detection and handling (EDH) according to SMPTE RP-165. Interfacing to the parallel inputs of either the GS9002, GS9022 or GS9032 serial digital encoders, the GS9021A is primarily used on the transmit end of the SDI interface. The GS9021A provides EDH insertion and extraction for 4ƒsc NTSC, 4ƒsc PAL and all component PAL and NTSC standards including 4:2:2 (13.5MHz and 18MHz luminance sampling), and 4:4:4:4.
The GS9021A generates noise immune timing signals such as horizontal sync, vertical blanking and field ID. In addition, TRS-ID correction/insertion and data blanking are implemented for all standards.
A host interface, configurable as an 8-bit parallel interface or an I2C (I2C is a registered trademark of Philips) serial interface allows for communication with a microcontroller. The interface can be used to read and/or write the complete set of error flags and override the flag status prior to re-transmission. A 5-bit flag port provides access to all error flags on dedicated pins for applications where the microcontroller is not used. The device automatically determines the operating standard, but this can be overridden through the programming interface.
- Error Detection and Handling (EDH) according to SMPTE RP-165
- drop-in replacement for the GS9021
- EDH insertion and extraction in one device
- auto-standard operation with override via host interface
- noise immune extraction of HVF timing signals
- TRS insertion/correction and ANC header correction for all standards
- ITU-R-601 output clipping for active picture area
- selectable I2C interface or 8-bit parallel port for access to EDH flags and device configuration bits
- all error flags available on dedicated output pins
- 24-bit Errored Field counter
- BYPASS mode to bypass EDH insertion/updating
- dynamic blanking control input
- 8-bit or 10-bit compatibility
- up to 54MHz operating frequency
- seamless flag-mapping with GS9020 serial digital video input processor
EDH processing for SMPTE 259M serial digital interfaces for composite and component standards including 4:4:4:4 at 540Mb/s; Noise immune digital sync and timing generation. Source, destination, distribution and test equipment; General purpose, TRS formatted, blank video stream generator with EDH.
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