GS9000D
Serial Digital Decoder
Description
Features
Applications
Downloads
The GS9000D is a CMOS integrated circuit specifically designed to deserialize SMPTE 259M serial digital signals at data rates up to 270Mb/s. The GS9000D is a pin and functional equivalent to the GS9000C, with the exception of SDI input levels which are compatible for direct interfacing to the GS7025, GS9025A and GS9035A.
The device incorporates a descrambler, serial to parallel convertor, sync processing unit, sync warning unit and automatic standards select circuitry.
Differential pseudo-ECL inputs for both serial clock and data are internally level shifted to CMOS levels. Digital outputs such as parallel data, parallel clock, HSYNC, Sync Warning and Standard Select are all TTL compatible.
The GS9000D is packaged in a 28 pin PLCC and operates from a single 5 volt, ±5% power supply.
- fully compatible with SMPTE 259M-ABC
- decodes 8 and 10-bit serial digital signals for data rates to 270Mb/s
- recommended alternative to GS9000C for use when interfacing directly to GS7025, GS9025A or GS9035A
- incorporates automatic standards selection
- 325mW power dissipation at 270MHz clock rate
- operates from single +5 or -5 volt supply
- 28 pin PLCC packaging
4ƒSC and 4:2:2 serial digital interfaces
Automatic standards select controller for serial routing and distribution applications
Ordering Information| Part No | Package | GS9000DCPJ
| 28 pin PLCC | GS9000DCTJ
| 28 pin PLCC Tape | GS9000DCPJE3
| 28 pin PLCC | GS9000DCTJE3
| 28 pin PLCC Tape |
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